Time multiplexed processor bus
US4630193A · kind A · utility
100Cited by
14References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1982 |
| Grant date | Dec 16, 1986 |
| Priority date | — |
| Expiry date | Sep 23, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/372
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-master processor bus and a method of processing data which permits multiple microprocessors to communicate freely and inexpensively among themselves and various system resources. The bus uses a multiphase clock and latches to provide time slice signals to sequentially activate each processor, one at a time in a repetitive sequence. The bus includes cables and terminals for each of the cables with means for interconnecting each of the modules in series daisy chain fashion to selected cables.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.