Battery saving system for a frequency synthesizer
US4631496A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1985 |
| Grant date | Dec 23, 1986 |
| Priority date | — |
| Expiry date | Dec 13, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/405
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. A battery saving circuit generates a battery saving signal having a predetermined duty cycle and period and is responsive to the phase detector in the synthesizer to disrupt power to the synthesizer while maintaining precise tuning. The battery saver circuit is also responsive to the transceiver. In a normal receive operation, a battery saving circuit synchronizes its battery saving signal with the hold condition of the phase detector to disrupt power to selected modules in the synthesizer without altering the injection frequency of the receiver. In a standby mode, power is disrupted to all modules in the receiver, the selected modules in the phase locked loop and the voltage controlled oscillator. During a transmit mode all battery saving is terminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.