Memory interface with automatic delay state
US4631659A · kind A · utility
60Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1985 |
| Grant date | Dec 23, 1986 |
| Priority date | — |
| Expiry date | Apr 1, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital processor system that includes a processor interface to an external memory. The interface to the external memory includes an information transfer bus to transfer information between the processor and the external memory and control circuitry to regulate the information on the information bus. This control circuitry includes the capability to delay the reading of information on the memory in order to allow for memory accesses to a slow memory. This delay capability is a selectable feature that is selected upon initialization of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.