Interrupt level sharing
US4631670A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1984 |
| Grant date | Dec 23, 1986 |
| Priority date | — |
| Expiry date | Jul 11, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt interface circuit for interrupt level sharing comprising a pulse generator having an open-collector or tri-state output connected to an external interrupt line shared by other similar circuits. An active internal interrupt signal causes the pulse generator to pulse. The external interrupt line is fed back and latched on a disabling input of the pulse generator so that any pulse on the external interrupt line prevents further pulsing. The software handler of the interrupt, upon servicing an interrupt of the interrupt level, causes the enabling of the pulse generators of that level, thereby permitting active internal interrupt signals to produce a further pulse. By this interrupt level sharing, phantom interrupts are eliminated and servicing overhead is minimized. R
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.