Self biasing direct coupled data limiter
US4631737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1984 |
| Grant date | Dec 23, 1986 |
| Priority date | — |
| Expiry date | Dec 6, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interface circuit is coupled between the last stage of an FSK receiver and a limiter to provide a biasing voltage signal to the limiter. The receiver includes a power saver circuit which supplies power on an interrupted basis. The interface circuit contains maximum and minimum detectors which derive and hold voltages corresponding to the maximum and minimum values of the discriminated signal from the receiver. These maximum and minimum corresponding voltages are averaged in a predetermined manner to provide the biasing voltage to the limiter. Thus, a proper bias voltage level can be accurately and quickly determined, and supplied to the limiter when power is supplied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.