DC offset correction circuit utilizing switched capacitor differential integrator
US4633223A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 1985 |
| Grant date | Dec 30, 1986 |
| Priority date | — |
| Expiry date | May 28, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit employing a differential integrator and switched capacitor network to provide auto-zeroing. The differential integrator utilizes a feedback circuit between its inputs and outputs. A switched capacitor network coupled to the inputs of the amplifier provides voltage division of differential reference signals which determine the amount of DC offset. The amplifier then integrates the reference signals to a predetermined time constant, wherein the average voltage of the output of the integrator is used to provide auto-correction of the DC offset. A second switched capacitor voltage divider network and a second differential integrator cascaded to the first circuit provides a second time constant for fine-tuning the auto-correction signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.