Fault detection and redundancy management system
US4634110A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1983 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Jul 28, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault detection and redundancy management system for a dual redundancy based network architecture in which the principal control components (master units) are configured and programmed to repetitively carry out intra- and inter-unit performance tests as an a priori requirement for network command capability. These performance tests are carried out in a prescribed sequence to define the fault detection and reconfiguration procedure. The procedure is designed to preclude the cascading of faults. As a first step in this procedure, each processor in a master unit performs a thorough self-test of its own functional capability. Secondly, if a processor has determined that it has passed all of these internal procedures, it must then successfully inform a designated "chief" processor via an interprocessor handshake. This interprocessor handshake is effected by causing each processor in the master unit to set a flag in a shared memory during a prescribed time interval. These flags are read by the chief processor to determine whether to enable an associated bus controller for the next succeeding time interval, and once these flags have been read they are reset by the chief processor, as ea…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.