Method for planarizing the surface of an interlayer insulating film in a semiconductor device
US4634496A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1985 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Nov 14, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.