CMOS power-on reset circuit
US4634904A · kind A · utility
14Cited by
14References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 3, 1985 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Apr 3, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS reset circuit has a reverse biased diode and a latch for latching a p-channel enhancement mode MOSFET on during the first part of the power-on cycle. The p-channel MOSFET is part of a voltage divider which also includes a resistor. When the voltage between p-channel MOSFET and resistor reach the threshold of an n-channel enhancement mode MOSFET, the p-channel MOSFET is switched off. Reset pulses are provided through one or two inverters by a load on the latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.