Memory device
US4635083A · kind A · utility
10Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 10, 1986 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Apr 10, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/05
Abstract
A memory device includes a relative lower bandgap energy first semiconductor layer, a relatively higher bandgap energy second semiconductor layer on the first, an alloy source rectifying to the first layer, a well for storing charge and a gate for controlling charge flow between the source and the well. The gate is formed on the second layer, as is a field plate for controlling the storage charge in the well. In one embodiment, a buried channel field effect transistor is combined with the basic memory device, with the charge content of the well controlling current flow between the source and drain of the buried channel FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.