Video signal delay circuit
US4635116A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1985 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Feb 26, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A video signal delay circuit comprises an input horizontal transfer register supplied serially with an input composite video signal, an input vertical transfer gate, a plurality of columns of vertical transfer registers, an output vertical transfer gate, an output horizontal transfer register, a horizontal transfer clock pulse generating circuit, a vertical transfer clock pulse generating circuit and a vertical transfer gate pulse generating circuit. The vertical transfer clock pulse generating circuit generates a vertical transfer clock pulse at a rate of once per one horizontal scanning period of the input composite video signal and additionally generates one or more vertical transfer clock pulses during a specific time period. Or, the horizontal transfer clock pulse generating circuit generates a horizontal transfer clock pulse having a selected phase or a selected number of horizontal transfer clock pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.