Integrated dynamic write-read memory with a decoder blocking the data path from the memory matrix

US4635190A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Willibald Meyer · Hersbruck, DE
• Jurgen Wawersig · Munich, DE

Key dates

• Filing date: Mar 23, 1984
• Grant date: Jan 6, 1987
• Expiry date: Mar 23, 2004

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/835
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated dynamic write-read memory includes at least one redundant row and/or column initially excluded from normal operation of the memory but available for normal operation as a replacement. At least one row decoder is connected to the memory matrix and at least one column decoder is connected to the memory matrix for addressing. A column address pulse is fed to the memory matrix for initiating addressing by matrix columns and a row address pulse is fed to the memory matrix for initiating addressing by matrix rows. A normal data path leading out of the memory matrix includes a tristate output connected to the normal data path and actuated by addressing with the stored digital data. Another decoder is connected in the normal data path between the memory matrix and the tristate output with an output connected to the tristate output. The other decoder blocks the normal data path from the memory matrix to the tristate output upon addressing each row or column of the portion of the memory matrix intended for normal operation replaced by a redundant row or column and upon simultaneous external activation of the other decoder. The other decoder also indicates the insertion of a red…