Binary coded decimal number division apparatus
US4635220A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1983 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Nov 8, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4917
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.