Coherent interface with wraparound receive memory
US4635254A · kind A · utility
14Cited by
2References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1984 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Dec 13, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface for use between an asynchronous bus and a signal processor is disclosed. The interface utilizes a wraparound receive memory to ensure coherency with very little processor overhead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.