Digital clock recovery circuit apparatus
US4635277A · kind A · utility
15Cited by
3References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1985 |
| Grant date | Jan 6, 1987 |
| Priority date | — |
| Expiry date | Oct 21, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital circuit which ascertains the middle of a digital pulse by first determining its total length through digital logic means in combination with a digital signal delay means, and uses this information to operate a state machine (or sequencer), which will assume that data clocks occur at the time of the last received valid data pulse until new logic "1" data is received, and at this time can be resynchronized or phase-locked if there is a time discrepancy between recently received data and the status of the state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.