Method and apparatus for monitoring automated testing of electronic circuits
US4637020A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 17, 1984 |
| Grant date | Jan 13, 1987 |
| Priority date | — |
| Expiry date | May 17, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/0026
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested. Other features are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.