Process for fabricating semiconductor integrated circuit device
US4637124A · kind A · utility
17Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1985 |
| Grant date | Jan 20, 1987 |
| Priority date | — |
| Expiry date | Mar 18, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.