CMOS bias voltage generating circuit
US4638184A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 13, 1984 |
| Grant date | Jan 20, 1987 |
| Priority date | — |
| Expiry date | Sep 13, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/465
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A bias generating circuit for reducing an external DC power supply voltage to a predetermined, lower, stable DC voltage used as a power source for internal logic circuits in a semiconductor IC chip includes an oscillator for converting the external DC voltage into a pulse signal, a smoothing circuit for converting a pulse signal into the lower DC voltage, and a control circuit interposed between the oscillator and the smoothing circuit for varying the pulse duration of the pulse signal from the oscillator to a changed pulse signal, and for regulating the lower DC voltage to a predetermined amplitude in response to the voltage variation in the lower DC voltage. The control circuit comprises a CMOS inverter, a CMOS buffer circuit for varying the pulse duration of the output signal of the CMOS inverter, and a voltage compensating circuit for controlling the transconductance of the CMOS inverter in response to the variation of the lower DC voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.