Fast and gate with programmable output polarity
US4638189A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1984 |
| Grant date | Jan 20, 1987 |
| Priority date | — |
| Expiry date | Jun 29, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/666
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead. Thus, either the once inverted signal is provided to the output lead or the twice inverted signal is provided to the output lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.