Multiplier architecture
US4638449A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 1985 |
| Grant date | Jan 20, 1987 |
| Priority date | — |
| Expiry date | Aug 14, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved multiplier is disclosed for multiplying a first operand times a second operand, which includes a Booth-type translator having an input connected to receive the first operand, for translating the binary expression of the first operand into a sequence of signed digits. The multiplier further includes a partial product generator having a first input connected to the output of the translator and a second input connected to receive the second operand, for multiplying the translated first operand times the second operand and outputting partial products consisting of signed digits. The multiplier further includes an array of adders, each adder having an input connected to two of the signed digits output from the partial product generator, for providing a sum consisting of a sequence of signed digits. The multiplier further includes an inverse translator having an input connected to the output of the adders, for operating on the sequence of signed digits output from the adders, for providing a conventional binary expression for the product of the first and the second operands. The improved multiplier is capable of faster operation than has been available in the prior art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.