Random logic error detecting system for differential logic networks
US4638482A · kind A · utility
4Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1984 |
| Grant date | Jan 20, 1987 |
| Priority date | — |
| Expiry date | Dec 24, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0751
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for testing a differential logic network is provided which includes a differential exclusive OR circuit having a plurality of inputs for receiving complementary signals from the differential logic network and first and second output terminals and means, e.g., a conventional exclusive OR circuit, for determining the voltage difference between the first and second output terminals to indicate the presence or absence of a fault or error in the differential logic network under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.