Power transistor structure having an emitter ballast resistance
US4639757A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 1981 |
| Grant date | Jan 27, 1987 |
| Priority date | — |
| Expiry date | Dec 11, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/125
Abstract
In a semiconductor device a power transistor is equipped with a ballast resistance formed in the same semiconductor layer which forms the emitter regions which perform the bipolar transistor operation. Due to this ballast resistance and an electrode extension portion also formed in the emitter semiconductor layer, an undesirable parasitic transistor is also formed in the semiconductor device. This parasitic transistor is comprised of an emitter formed by the ballast resistor and the electrode extension portion, and the base and collector regions of the bipolar transistor layers which are immediately below the ballast resistor and the electrode extension portion. Accordingly, means are disposed in the layer forming the base region for reducing the current gain of the parasitic transistor. This current gain reducing means can include either an expanded width base portion or a higher impurity concentration base portion in the parasitic transistor region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.