High speed packet switching arrangement
US4641302A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 1985 |
| Grant date | Feb 3, 1987 |
| Priority date | — |
| Expiry date | Jun 24, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5649
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement is provided for switching serial data packets through a network destined for one of a plurality of possible outgoing lines. Minimal delay is achieved by shifting the data through a shift register having length equivalent to the destination address of the incoming serial data packet. The shift register addresses a memory which in turns controls a switch network so that the incoming packet is switched with minimal delay to an appropriate outbound line. By utilizing random access memory to translate from destination address to switch position, the system may be altered to correct for changes in the overall network caused by network failures or expansion network or to allow dynamic load balancing by directing data through the switch to a control computer which in turn rewrites the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.