Fabricating an integrated circuit device having a vertical pnp transistor
US4641419A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 1985 |
| Grant date | Feb 10, 1987 |
| Priority date | — |
| Expiry date | Mar 18, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for producing semiconductor devices with a high-performance vertical pnp transistor having a high h.sub.fe and a high f.sub.T, comprising a step for forming an impurity region of a high concentration in a portion of a p-type buried layer and for increasing the concentration in a diffusion layer for isolation, a step for forming an n-type well region that reaches the p-type buried layer and that serves as a base of the vertical pnp transistor, and a step for forming an emitter of the vertical pnp transistor in a portion of said n-type well region, and for forming a collector electrode contact portion of the vertical pnp transistor, said contact portion reaching said impurity region of high concentration, by introducing p-type impurities into a portion of the p-type buried layer that serves as a portion of the collector of the vertical pnp transistor and into the p-type diffusion layer that works as an isolation layer or channel stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.