Multiple phase clock buffer module with non-saturated pull-up transistor to avoid hot electron effects
US4642492A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1984 |
| Grant date | Feb 10, 1987 |
| Priority date | — |
| Expiry date | Oct 25, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1506
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock buffer circuit for multiple phase complementary clocking signals that receives a plurality of corresponding enabling signals and generates a like plurality of clock signals in response thereto. Each clocking signal is generated by a buffer module including a resistor, a pull-up transistor and a pull-down transistor, which are connected in series between a positive power supply and ground, with the clocking signal being taken from the node between the pull-up and pull-down transistors. In each module, before the clocking signal shifts from a low state to a high, the pull-down transistor is on so that the clocking signal is at a low state. The pull-up transistor in each module is controlled by the corresponding enabling signal and is enabled to begin conducting at the time that the clocking signal is to shift to a high state. The resistor keeps the pull-up transistor in its linear, non-saturated operating regions, which results in an increase in the intrinsic capacitance in the pull-up transistor from the saturated condition. After the pull-up transistor is turned on, allowing the intrinsic capacitance of the pull-up transistor to charge, the pull-down transistor is then turn…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.