Phase locked loop circuit for demodulating suppressed carrier signals
US4642573A · kind A · utility
26Cited by
1References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 3, 1985 |
| Grant date | Feb 10, 1987 |
| Priority date | — |
| Expiry date | Oct 3, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0031
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop circuit for use in a heterodyne receiver for stably demodulating a carrier-suppressed double-sideband signal such as a 2-phase or 4-phase PSK signal. The phase locked loop circuit comprises a reference oscillator oscillating at a frequency corresponding to an intermediate frequency, and the frequency difference between the reference frequency and the input frequency is detected by a Costas loop, a signal indicative of the frequency difference being fed back to a local oscillator through a loop filter thereby stabilizing the intermediate frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.