Graph manager for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
US4644464A · kind A · utility
7Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1984 |
| Grant date | Feb 17, 1987 |
| Priority date | — |
| Expiry date | Jun 5, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4494
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel register-transfer mechanism and control section have been disclosed above for use in a reduction process for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.