Apparatus for controlling I/O interrupt in multiprocessor system
US4644465A · kind A · utility
21Cited by
3References
3Claims
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Key dates
| Filing date | Jun 21, 1984 |
| Grant date | Feb 17, 1987 |
| Priority date | — |
| Expiry date | Jun 21, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for controlling interrupts is provided in a system controller SC of a multiprocessor system in which a plurality of instruction processors IP share a main storage MS and a channel controller CHC through the system controller SC. The apparatus for controlling interrupts holds I/O interrupt control data for each of the instruction processors IP, and selects the most suitable instruction processor IP to process an I/O interrupt, without receiving responses from all of the instruction processors IP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.