DC level trip detector
US4645881A · kind A · utility
49Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1984 |
| Grant date | Feb 24, 1987 |
| Priority date | — |
| Expiry date | Oct 19, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M19/026
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The method includes generating a binary signal (S4A to S4D) which is time modulated. To do this, an alternating signal (S1) is compared with a known cyclical signal (S5) and a threshold signal. There is measured the durations between the transitions of the modulated signal by means of a high speed clock and by means of counting in the positive and negative directions of the clock pulses for one or more periods of the signal under examination. If, after counting, a residual value is found, one generates a binary signal representing the transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.