Digital multiplication circuit for use in a microprocessor
US4646257A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1983 |
| Grant date | Feb 24, 1987 |
| Priority date | — |
| Expiry date | Oct 3, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier. Each operation set is applied to a second plurality of n partial products selectors which are connected in cascade arrangement according to multiplicand sets and wherein each partial product selector multiplicand set implements one of the recoded Booth operation sets. The outputs of the partial product selectors are summed by a summation means and a domino circuit means provides an evaluation pulse for each member of the partial product selector at the completion of the Booth operation set that is connected to the partial product selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.