Data collection terminal high speed communication link interrupt logic
US4646260A · kind A · utility
6Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1983 |
| Grant date | Feb 24, 1987 |
| Priority date | — |
| Expiry date | Oct 3, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. Included among the devices is a communication controller. An interrupt controller processes the device interrupt requests by sending out a vector address to the microprocessor. This enables the microprocessor to branch to a subroutine to process the interrupt. Apparatus is provided to enable the communication controller to generate vector addresses when it sends an interrupt request to the interrupt controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.