Parasitic insensitive switched capacitor input structure for a fully differential operational amplifier
US4647865A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 1986 |
| Grant date | Mar 3, 1987 |
| Priority date | — |
| Expiry date | Feb 20, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input structure which is parasitic insensitive and allows a fully differential amplifier to receive a single input voltage while maintaining a predetermined common-mode input voltage is provided. A single input voltage is charged onto two capacitors which are coupled in series between the input voltage and a predetermined common-mode reference voltage terminal during a first time period. During a second time period, the two capacitors are reconfigured so that each capacitor is connected between the reference voltage terminal and a predetermined one of the inputs of the fully differential amplifier. Due to the balanced nature of the input structure, all parasitic capacitance error terms are rejected by the differential amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.