Back biased CMOS device with means for eliminating latchup

US4647956A · kind A · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Rituparna Shrivastava · Denton, US
• Raymond E. Bloker · San Jose, US
• Fred Jenne · Los Gatos, US

Key dates

• Filing date: Feb 12, 1985
• Grant date: Mar 3, 1987
• Expiry date: Feb 12, 2005

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a "hot-socket" connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.