Latchup-preventing CMOS device
US4647957A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1986 |
| Grant date | Mar 3, 1987 |
| Priority date | — |
| Expiry date | Apr 21, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/763
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.