Cache invalidation mechanism for multiprocessor systems
US4648030A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1983 |
| Grant date | Mar 3, 1987 |
| Priority date | — |
| Expiry date | Sep 22, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68). In this way, non-path accesses of a local memory can be permitted, yet proper invalidation of cache memories can be performed in a simple manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.