Bus interface device for a data processing system
US4648102A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1984 |
| Grant date | Mar 3, 1987 |
| Priority date | — |
| Expiry date | Mar 5, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines. The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7. The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.