Circuit arrangement for telecommunications exchange systems, particularly telephone exchange systems, comprising information processing sequential logic systems and traffic measuring devices
US4649234A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1985 |
| Grant date | Mar 10, 1987 |
| Priority date | — |
| Expiry date | Jul 11, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/54591
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for telecommunications exchange systems, particularly telepone exchange systems, comprising information processing sequential logic systems and traffic measuring devices, is provided for handling processing requests. Processing requests are marked by a sequential logic systems as partially acceptable and input into a waiting list formed as a FIFO buffer. Processing requests marked not acceptable are input into a FIFO-LIFO memory which ejects a processing request in a FIFO mode when it is full and when the waiting list is at least partially filled and marks them as not acceptable, but marks processing requests as acceptable and outputs the same to the waiting list in the LIFO mode when the waiting list is empty or nearly empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.