PNPN semiconductor switches
US4649414A · kind A · utility
9Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1985 |
| Grant date | Mar 10, 1987 |
| Priority date | — |
| Expiry date | Sep 18, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
In a planer type PNPN semiconductor switch having a MOS FET structure, a field plate electrode is embedded in an insulator covering a surface of a semiconductor substrate to overlie an interface between the semiconductor substrate and a P gate region for limiting an extention of a depletion layer from an anode region to a P gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.