Video signal delay circuit
US4649427A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 5, 1985 |
| Grant date | Mar 10, 1987 |
| Priority date | — |
| Expiry date | Mar 5, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A video signal delay circuit comprises a plurality of rows of input horizontal transfer registers, a plurality of input vertical transfer gates, a plurality of columns of vertical transfer registers, a plurality of output vertical transfer gates, a plurality of rows of output horizontal transfer registers, a horizontal transfer clock pulse generating circuit, a vertical transfer clock pulse generating circuit, and a selecting circuit. The selecting circuit selectively supplies a horizontal transfer clock pulse to an arbitrarily selected one of the plurality of rows of input horizontal transfer registers and to an arbitrarily selected one of the plurality of rows of output horizontal transfer registers based on at least horizontal and vertical synchronizing signals within an input composite video signal. The selecting circuit supplies the input composite video signal to the arbitrarily selected one of the plurality of rows of input horizontal transfer registers and selectively obtains an output composite video signal of only the arbitrarily selected one of the plurality of rows of output horizontal transfer registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.