Dynamic memory controller for single-chip microprocessor
US4649511A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 1983 |
| Grant date | Mar 10, 1987 |
| Priority date | — |
| Expiry date | Jul 25, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe-generation and multiplexing subcircuits to burst-refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.