Semiconductor integrated circuit

US4651190A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Hiroaki Suzuki · Toyokawa, JP
• Teruo Kobayashi

Key dates

• Filing date: Oct 17, 1985
• Grant date: Mar 17, 1987
• Expiry date: Oct 17, 2005

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A semiconductor integrated circuit includes p- and n-type semiconductor areas alternately arranged in a row direction, p-channel MOS transistor blocks arranged in each of the p-type semiconductor areas and each including two p-channel MOS transistors, n-channel MOS transistor blocks arranged in each of the n-type semiconductor areas and each including two n-channel MOS transistors, and p- and n-type diffusion areas formed, respectively, in each of the p-type semiconductor areas and in each of the n-type semiconductor areas. The MOS transistor blocks are arranged on two columns in each of the p- and n-type semiconductor areas, and each of the diffusion areas is formed in a position defined by the gate electrodes of four MOS transistors of the same channel type in the two MOS transistor blocks adjacent to each other in a row direction.