Semiconductor memory device
US4653027A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1984 |
| Grant date | Mar 24, 1987 |
| Priority date | — |
| Expiry date | Dec 3, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device operated synchronously with clock signals, such as a MOS dynamic RAM device. The semiconductor memory device includes a switch circuit inserted between a prestage output amplifier circuit receiving a readout signal from a memory cell and an output buffer circuit. The switch circuit is turned on just before the output signal is supplied from the prestage output amplifier circuit to the output buffer circuit and turned off after the output condition of the output buffer circuit is settled. The potential corresponding to the output data is maintained in the circuit between the switch circuit and the output buffer circuit. The output condition of the output buffer circuit is therefore retained even during the reset period of the prestage drive circuit, and the duration period of the output signal is expanded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.