Fabrication process for aligned and stacked CMOS devices

US4654121A · kind A · utility

Assignee

• NCR Corporation · US

Inventors

• Gayle W. Miller · Colorado Springs, US
• Nicholas J. Szluk · Fort Collins, US
• William W. McKinley · Fort Collins, US
• Hubert O. Hayworth · Fort Collins, US
• George Maheras · Fort Collins, US

Key dates

• Filing date: Feb 27, 1986
• Grant date: Mar 31, 1987
• Expiry date: Feb 27, 2006

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A process for fabricating aligned, stacked CMOS devices. Following the formation of the lower FET device, conformal undoped and doped oxide layers are formed thereover so that the level of the upper surface of the common gate electrode is above the doped oxide as formed in the source and drain regions of the lower FET device. A planarizing photoresist is then deposited and etched in conjunction with the oxide to the upper surface of the gate electrode. The exposed gate electrode is covered with a gate oxide layer, and a polycrystalline silicon layer for recrystallization to an upper FET device. Updiffusion from the residuals of doped oxide then creates an upper FET device with source and drain regions aligned to the gate oxide thereof and the underlying common gate electrode.