Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
US4654780A · kind A · utility
11Cited by
1References
8Claims
0Family size
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Key dates
| Filing date | Jun 5, 1984 |
| Grant date | Mar 31, 1987 |
| Priority date | — |
| Expiry date | Jun 5, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4494
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel register-transfer mechanism has been disclosed above for use in the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expression is reduced through a series of transformations until a result is obtained. A register file is provided with several crossbar networks interconnecting the various registers in the file for simultaneous transfer of their contents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.