Asynchronous multiport parallel access memory system for use in a single board computer system
US4654788A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1983 |
| Grant date | Mar 31, 1987 |
| Priority date | — |
| Expiry date | Jun 15, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes an asynchronous parallel multiport volatile main memory system accessible directly by any one of M number of central processing units or by I/O controllers connected in common to any one of N number of system buses. Priority resolver circuits award access to main memory on a predetermined priority basis. Each port includes address, data in, data out, timing and control circuits which operatively couple to the priority resolver circuits. The circuits of each port and the central processing unit or system bus I/O controllers associated therewith operate independently of each other in an asynchronous manner to access and store data and to report errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.