Translation of virtual and real addresses to system addresses
US4654790A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 28, 1983 |
| Grant date | Mar 31, 1987 |
| Priority date | — |
| Expiry date | Nov 28, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus translates a set of logical addresses to a system addresses where the set of logical addresses includes virtual and real addresses which map to the same system address. An address mechanism provides a requesting field for indicating when a requesting logical address is virtual or when a requesting logical address is real. An address translator translates logical addresses to system addresses. A translation buffer stores translation information for associating logical addresses with system addresses. The translation buffer includes means for storing a resident field for indicating if stored translation information associates a virtual address with a system address, a real address with a system address, or both a real address and a virtual address with a system address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.