Method and structure for disabling and replacing defective memory in a PROM
US4654830A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1984 |
| Grant date | Mar 31, 1987 |
| Priority date | — |
| Expiry date | Nov 27, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages. The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.