Self-aligned recessed gate process

US4656076A · kind A · utility

Assignee

• TriQuint Semiconductor, Inc. · US

Inventors

• William A. Vetanen · Hillsboro, US
• Kimberly R. Gleason · Portland, US
• Irene G. Beers · Tigard, US

Key dates

• Filing date: Apr 26, 1985
• Grant date: Apr 7, 1987
• Expiry date: Apr 26, 2005

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T428/258

Abstract

An integrated circuit gate process and structure are disclosed which provide a self-aligned, recessed gate enhancement-mode GaAsFET. The process includes making self-aligned implants prior to gate metallization, with an intermediate step of applying patches of plasma- and chemical-etch resistant dielectric, such as zirconium oxide (ZrO), over the self-aligned implants to fixedly define gate length. The self-aligned gate process includes stair-stepping three successive implants, in respect to both depth and concentration, to provide a dopant concentration gradient inclined depthwise away from each side of the gate. The self-aligned, recessed gate GaAsFET exhibits improved source-gate resistance without degradation of gate-drain capacitance, increased gain and drain-source current, and reduced knee-voltage. Gate length is minimized to the limits of photolithography without degrading input resistance.