Patent · US Expired

Device in the instruction unit of a pipeline processor for instruction interruption and repetition

US4656578A · kind A · utility

19Cited by

2References

5Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Herbert Chilinski · Schenefeld, DE
Klaus J. Getzlaff · Schenefeld, DE
Johann Hajdu
Stephan Richter · Neubiberg, DE

Key dates

Filing date	Sep 4, 1984
Grant date	Apr 7, 1987
Priority date	—
Expiry date	Sep 4, 2004

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/141
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In the processing of instructions in data processing systems it is not always possible to execute these instructions without interruption since particular situations, in the following called events can occur which necessitate a short interruption for executing the operations caused by such events before continuing the interrupted instruction processing. Such repetition however is only possible when the contents of the operation register containing the instruction is frozen during the interruption. Such a situation requires two actions: the first is the execution of a forced operation to resolve the event. The second action is a repetition of the instruction and execution phase of the interrupted instruction.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.