Video system controller with a row address override circuit
US4656597A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1984 |
| Grant date | Apr 7, 1987 |
| Priority date | — |
| Expiry date | Jul 23, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video system is able to change the display on a video monitor with a minimal number of memory transfer cycles. The video system includes a monitor for displaying of processed data, a processor means for processing the data to be displayed, a display memory means divided into a plurality of planes addressable by a row address, the display memory stores the data that has been processed by the processor means. There are additional other sources of data which is processed by the processor means for storing in the display memory and subsequently being displayed by the CRT monitor . A control means controls the data transfer between the data sources, the processor, the display memories, and the CRT monitor and includes a row address override circuit. The row address override circuit comprises a plurality of output logic for providing a write enable signal to a memory plane. Each memory plane is connected to a cross finding output logic circuit. A select means selects a source of data that is to be written to the memory plane, and an override means provides a write enable to a preselected number of memory planes simultaneously with the same predetermined number of output logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.